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e - cmos corp. ( www.ecmos.com.tw ) page 1 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash general description the ECT25S40 is 4m - bit serial peripheral interface(spi) flash memory, and supports the dual/quad spi: ser ial clock, chip select, serial data i/o0 (si),i/o1(so),i/o2(/wp), and i/o3 (/hold). the dual i/o data is transferred with speed of 2 16mbits/s and the quad i/o & quad output data is transferred with speed of 432mbits/s. the device uses a single low voltage power supply, ranging from 2.7 volt to 3.6 volt. additionally ,the device supports jedec standard manufacturer and device id and t hree 256 - bytes security registers. in order to meet enviro nmental requiremen ts, e - cmos offers an 8 - pin so p 150 mil,208mil , 8 - pin tssop an d 8 - pin df n 6x5 - mm,and other special order packages . features serial peripheral interface(spi) - standard spi: sclk, /cs, si, so, /wp, /hold - dual spi: sclk, /cs, io0, io1, /wp, /hold - quad spi: sclk, /cs, io0, io1, io2, io3 read - normal read (serial): 50mhz clock rate - fast read (serial): 108mhz clock rate - dual/quad (multi - i/o) read: 108mhz clock rate program - serial - input page program up to 256bytes - program suspend and resume erase - block erase (64/32 kb) - sector erase (4 kb) - chip erase - erase suspend and resume program/erase speed - p ag e program time: 0.7ms typical - sector erase time: 60ms typical - block erase time: 0.3/0.5s typical - chip erase time: 4s typical flexible architecture - sector of 4k - byte - block of 32/64k - byte low power consumption - 20ma maximum active current - 5ua maximum power down current
e - cmos corp. ( www.ecmos.com.tw ) page 2 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash software/hardware write protection - 3x256 - byte security registers with otp lock - enable/disable protection with wp pin - write protect all/portion of memory via software - top or bottom, sector or block selection sin gle supply voltage - full voltage range: 2.7~3.6v temperature range - commercial (0 to +70 ) - industrial ( - 40 to +85 ) cycling endurance/data retention - typical 100k program - erase cycles on any sector - typical 20 - year data retention at +55 fig ure 1. logic diagram figure 2. pin configuration s op 150/208 mil, tssop173mil
e - cmos corp. ( www.ecmos.com.tw ) page 3 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash figure 3. pin configuration dip8l signal description during all operations, vcc must be held stable and within the specified valid range: vcc(min) to vcc(max) all of the input and output signals must be held high or low (according to voltages of vih, voh, vil or vol s ee section dc electrical characteristics ).these signals are described next. input / output summary table 1. signal names chip select (/cs) the chip select signal indicates when a instruction for the device is in process and the other signals are relevant for the memory device.when the /cs signal is at the logic high state, the device is not selected and all input signals ar e ignored and all output signals are high impedance. unless an internal program, erase or write status registers embedded operation is in progress, the device will be in the standby power mode. driving the /cs input to logic low state enables the device, p lacing it in the active power mode. after power up, a falling edge on /cs is required prior to the start of any instruction. pin name i/o descri ption /cs i chip select so (io1) i/o serial output for single bit data instructions. io1 for dual or quad instructions. /wp (io2) i/o write protect in single bit or dual data instructions. io2 in quad mode. the signal has an internal pull - u p resistor and may be left unconnected in the host system if not used for quad instructions. vss ground si (io0) i/o serial input for single bit data instructions. io0 for dual or quad instructions. sclk i serial clock /hold (io3 ) i/o hold (pause) serial transfer in single bit or dual data instructions. io3 in quad - i/o mode. the signal has an internal pull - up resistor and may be left unconnected in the host system if not used for quad instructions. vcc core and i/o power supply
e - cmos corp. ( www.ecmos.com.tw ) page 4 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash serial clock (sclk) this input signal provides the synchronization reference for the spi interface. instructions, addresses, or data input are latched on the rising edge of the sclk signal. data output changes after the falling edge of sclk. serial input (si)/io0 this input signal is used to transfer data serially into the device. it receives instructions, addresses, and data to b e programmed. values are latched on the rising edge of serial sck clock signal. si becomes io0 an input and output during dual and quad instructions for receiving instructions, addresses, and data to be programmed (values latched on rising edge of serial sck clock signal) as well as shifting out data (on the falling edge of sck). serial data output (so)/io1 this output signal is used to transfer data serially out of the d evice. data is shifted out on the falling edge of the serial sck clock signal. so bec omes io1 an input and output during dual and quad instructions for receiving instructions, addresses, and data to be programmed (values latched on rising edge of serial sck clock signal) as well as shifting out data (on the falling edge of sck). write pro tect (/wp)/io2 when /wp is driven low (vil), while the status register protect bits (srp1andsrp0) of the status registers (sr2[0] and sr1[7]) are set to 0 and 1 respectively, it is not possible to write to the status registers. this prevents any alteration of the status registers. as a consequence, all the data bytes in the memory area that are protected by the block protect, tb, sec, and cmp bits in the status registers, are also hardware protected against data modification while /wp remains low. the /wp f unction is not available when the quad mode is enabled (qe) in status register 2 (sr2[1]=1). the /wp function is replaced by io2 for input and output during quad mode for receiving addresses, and data to be programmed (values are latched on rising edge of the sck signal) as well as shifting out data (on the falling edge of sck). /wp has an internal pull - up resistance; when unconnected; /wp is at vih and may be left unconnected in the host system if not used for quad mode. hold (/hold)/io3 the /hold signal goes low to stop any serial communications with the device, but doesnt stop the operation of wire staus register, programming, or erasing in progress. the operation of hold,need /cs keep low, and starts on falling edg e of the /hold signal, with sclk sig nal being low (if sclk is not being low, hold operation will not start until sclk being low). the hold condition ends on rising edge of /hold signal with sclk being low (if sclk is not being low, hold operation will not end until sclk being low). the hol d condition starts on the falling edge of the hold (/hold) signal, provided that this coincides with sck being at the logic low state. if the falling edge does not coincide with the sck signal being at the logic low state, the hold condition starts whene ver the sck signal reaches the logic low state.taking the /hold signal to the logic low state does not terminate any write, program or erase operation that is currently in progress. vcc power supply vcc is the supply voltage. is the single voltage used for all device functions including read, program, and erase.
e - cmos corp. ( www.ecmos.com.tw ) page 5 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash vss ground vss is the reference for the vcc supply voltage. block/sector addresses table 2. block/sector addresses of ECT25S40 notes: 1. block = uniform block, and the size is 64 k bytes. 2. half block = half uniform block, and the size is 32k bytes. 3. sector = uniform sector, and the size is 4k bytes. memory density block(64k byte) block(32k byte) sector no. sector s ize(kb) address range 4mbit block 0 half block 0 sector 0 4 000000h - 000fffh sector 7 4 007000h - 007fffh half block 1 sector 8 4 008000h - 008fffh 4 sector 15 4 00f000h - 00ffffh block 1 half block 2 sector 16 4 010000h - 010fffh sector 23 4 017000h - 017fffh half block 3 sector 24 4 018000h - 018ff fh sector 31 4 01f000h - 01ffffh block 6 half block 12 sector 96 4 060000h - 060fffh sector 103 4 067000h - 067fffh half block 13 sector 104 4 068000h - 068fffh sector 111 4 06f000h - 06ffffh block 7 half block 14 sector 112 4 070000h - 070fffh sector 119 4 077000h - 077fffh half block 15 sector 120 4 078000h - 078fffh sector 127 4 07f000h - 07ffffh
e - cmos corp. ( www.ecmos.com.tw ) page 6 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash spi operation standard spi instructions the ECT25S40 features a serial peripheral interface on 4 signals bus: serial clock (sclk), chip select (/cs), serial data input (si) and serial data output (so). both spi bus mode 0 and 3 are supported. input data is latched on the rising edge of sclk and data shifts out on the falling edge of sclk. dual spi instructions the ECT25S40 supports d ual spi operation when using the dual output fast read and dual i/o fast read (3bh and bbh) instructions. these instructions allow data to be transferred to or from the device at two times the rate of the standard spi. when using the dual spi instructi on the si and so pins become bidirectional i/o pins: io0 and io1. quad spi instructions the ECT25S40 supports quad spi operation when using the quad output fast read, quad i/o fast read (6bh, ebh) instructions. these instructions allow data to be tran sferred t - o or from the device at four times the rate of the standard spi. when using the quad spi instruction the si and so pins become bidirectional i/o pins: io0 and io1, and /wp and /hold pins become io2 and io3. quad spi instructions require the non - v olatile quad enable bit (qe) in status register - 2 to be set. operation features supply voltage operating supply voltage prior to selecting the memory and issuing instruct ions to it, a valid and stable vcc voltage within the specified [vcc(min), vcc(max)] range must be applied (see operating ranges ). in order to secure a stable dc supply voltage, it is recommended to decouple the vcc line with a suitable capacitor (usually of the order of 10 nf to 100 nf) close to the vcc/vss package pins. this voltage mus t remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (tw). power - up conditions when the power supply is turned on, vcc rises continuously from vss to vcc. during this time, the chip select (/cs) line is not allowed to float but should follow the vcc voltage, it is therefore recommended to connect the /cs line to vcc via a suitable pull - up resistor. in addition, the chip select (/cs) input offers a b uilt - in safe ty feature, as the /cs input is edge sensitive as well as level sensitive: after power - up, the device does not become selected until a falling edge has first been detected on chip select (/cs). this ensures that chip select (/cs) must have b een high, prior to going low to start the first operation. device reset in order to prevent inadvertent write operations during power - up (continuous rise of vcc), a power on reset (por) circuit is included. at power - up, the device does not respond to any instruction until vcc has reached the power on reset thres hold voltage(this threshold is lower than the minimum vcc operating voltage define d in operating ranges ). when vcc has passed the por threshold, the device is reset.
e - cmos corp. ( www.ecmos.com.tw ) page 7 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash power - down at power - down (continuous decrease in vcc), as soon as vcc drops from the normal operating voltage to below the power on reset threshold voltage, the device stops responding to any be allowed to follow the voltage applied on vcc) and in standby power mode (that is there should be no internal write cycle in progress). active power and standby power modes when chip select (/cs) is low, the device is selected, and in the active power mode. the device consumes icc. when chip select (/cs) is high, the device is des elected. if a write cycle is not currently in progress, the device then goes in to the standby power mode, and the device consumption drops to icc1. hold condition the hold (/hol d) signal is used to pause any serial communications with the device without resetting the clocking sequence. during the hold condition, the serial data output(so)is high impedance, and serial data input (si) and serial clock (sclk) are dont care. to enter the hold condition, the device must be selected, with chip select(/cs) lo w. normally, the device is kept selected, for the whole duration of the hold condition. deselecting the device while it is in the hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to res et any processes that had been in progress. the hold condition starts when the hold (/hold) signal is driven low at the same time as serial clock (sclk) already being low (as shown in figure 4). the hold condition ends when the hold (hold) signal is drive n high at the same time as serial clock (c) already being low. figure 4 also shows what happens if the rising and falling edges are not timed to coincide with serial clock (sclk) being low. figure 4. hold condition activation status register st atus register table see table 3 and table 4 for detail description of the status register bits. status register - 2 (sr2) and status register - 1 (sr1) can be used to provide status on the availability of the flash memory array, if the device is write enabl ed or disabled the state of write protection, quad spi setting, security register lock status, and erase/program suspend status.
e - cmos corp. ( www.ecmos.com.tw ) page 8 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash table 3. status register - 2 (sr2) table 4. status register - 1 (sr1) bit name function default value description 7 sus suspend status 0 0 = erase/program n ot suspended 1 = erase/program suspended 6 cmp complement protect 0 0 = normal protection map 1 = inverted protection map 5 lb3 security register lock bits 0 otp lock bits 3:1 for security registers 3:1 0 = security register not protected 1 = security re gister protected 4 lb2 0 3 lb1 0 2 reserved reserved 0 1 qe quad enable 0 0 = quad mode not enabled, the /wp pin and /hold are enabled. 1 = quad mode enabled, the io2 and io3 pins are enabled, and /wp and /hold functions are disabled 0 srp1 status resister protect 1 0 0 = srp0 selects whether /wp input has effect on protection of the status register 1 = srp0 selects power supply lock down or otp lock down mode bit name functio n default value description 7 srp0 status resister protect 0 0 0 = /wp input has no effect or power supply lock down mode 1 = /wp input can protect the status register or otp lock down 6 sec sector/block protect 0 0 = bp2 - bp0 protect 6 4kb blocks 1 = bp2 - bp0 protect 4kb sectors 5 tb top/bottom protect 0 0 = bp2 - bp0 protect from the top down 1 = bp2 - bp0 protect from the bottom up 4 bp2 block protect bits 0 000b = no protection see table 6 and table 7 for protection ranges 3 bp1 0 2 bp0 0 1 wel write enable latch 0 0 = not write enabled, no embedded operation can start 1 = write enabled, embedded operation can start 0 wip write in progress status 0 0 = not busy, no embedded operation in progress 1 = busy, embedded operation in pro gress
e - cmos corp. ( www.ecmos.com.tw ) page 9 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash the status and control bits wip bit the write in progress (wip) bit indicates whether the memory is busy in program/erase/write status register progress. when wip bit sets to 1, means the device is busy in program/erase/write status register prog ress, when wip bit sets 0, means the device is not in program/erase/write status register progress. wel bit the write enable latch bit indicates the status of the internal write enable latch. when set to 1 the internal write enable latch is s et, when set to 0 the internal write enable latch is reset and no write status register, program or erase instruction is accepted. sec, tb, bp2, bp1, bp0 bits the block protect (sec, tb, bp2, bp1, bp0) bits are non - volatile. they define the size of the a rea to be software protected against program and erase instructions. these bits are written with the write status register instruction. when the block protect (sec, tb, bp2, bp1, bp0) bits are set to 1,the relevant memory area(as defined in table 6 a nd table 7).becomes protected against page program, sector erase and block erase instructions. the block protect (sec, tb, bp2, bp1, bp0) bits can be written provided that the hardware protected mode has not been set. srp1, srp0 bits the status register p rotect (srp1 and srp0) bits are non - volatile read/write bits in the status register. the srp bits control the method of write protection: software protection, hardware protection, power supply lock - down or one time programmable protection. qe bit the qua d enable (qe) bit is a non - volatile read/write bit in the status register that allows quad operation. when the qe bit is set to 0 (default) the /wp pin and /hold pin are enable. when the qe pin is set to 1, the quad io2 and io3 pins are enabled. (the qe bit should never be set to 1 during standard spi or dual spi operation if the /wp or /hold pins directly to the power supply or ground). lb3/lb2/lb1 bit the lb bit is a non - volatile one time program (otp) bit in status register that provide the write pro tect control and status to the security registers. the default state of lb is 0, the security registers are unlocked. lb c an be set to 1 individually using the write register instruction. lb is one time programmable, once its set to 1, the 256byte securi ty registers will become read - only permanently, lb3/2/1 for security registers 3:1. cmp bit the cmp bit is a non - volatile read/write bit in the status register2 (bit6). it is used in conjunction the sec - bp0 bits to provide more flexibility for the array protection. please see the status registers memory protection table for details. the default setting is cmp=0. sus bit the sus bit is a read only bit in the status register2 (bit7) that is set to 1 after executing an erase/program suspend (75h) instructi on. the sus bit is cleared to 0 by erase/program resume (7ah) instruction as well as a power - down, power - up cycle.
e - cmos corp. ( www.ecmos.com.tw ) page 10 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash status register protect table table 5. status register protect table notes: 1. when srp1, srp0= (1, 0), a power - down, power - up cycle will change srp1, srp0 to (0, 0) state. 2.the one time programfeature is available upon special order. write protect fea tures 1. software protection: the block protect (sec, tb, bp2, bp1, bp0) bits define the section of the memory array that can be read but not change. 2. hardware protection: /wp going low to protected the bp0~sec bits and srp0~1 bits. 3.deep power - down: in deep power - down mode,all instructions are ignored except the release from deep power - down mode instruction. 4.write enable: the write enable latch(wel) bit must be set prior to every page program, sector erase, block erase, chip erase, write status registe r and erase/program security registers instruction. srp1 srp0 /wp status register description 0 0 x software protected t he status register can be written to after a write enable instruction, wel=1.(factory default) 0 1 0 hardware protected /wp=0, the status register locked and cannot be written. 0 1 1 hardware unprotected /wp=1, the status register is unlocked and can be written to after a write enable instruction, wel=1. 1 0 x power supply lock - down (1) status register is protected and cannot be written to again until the next power - down, power - up cycle. 1 1 x one time program (2) status r egister is permanently protected and cannot be written to.
e - cmos corp. ( www.ecmos.com.tw ) page 11 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash status register memory protection protect table table 6. status register memory protection (cmp=0) status register content memory content sec tb bp2 bp1 bp0 blocks addresses density p ortion x x 0 0 0 none none none none 0 0 0 0 1 7 070000h - 07ffffh 64kb upper 1/8 0 0 0 1 0 6 and 7 060000h - 07ffffh 128kb upper 1/4 0 0 0 1 1 4 to 7 040000h - 07ffffh 256kb upper 1/2 0 1 0 0 1 0 000000h - 00ffffh 64kb lower 1/8 0 1 0 1 0 0 and 1 000000h - 01 ffffh 128kb lower 1/4 0 1 0 1 1 0 to 3 000000h - 03ffffh 256kb lower 1/2 0 x 1 x x 0 to 7 000000h - 07ffffh 512kb all 1 0 0 0 1 7 07f000h - 07ffffh 4kb upper 1/128 1 0 0 1 0 7 07e000h - 07ffffh 8kb upper 1/64 1 0 0 1 1 7 07c000h - 07ffffh 16kb upper 1/32 1 0 1 0 x 7 078000h - 07ffffh 32kb upper 1/16 1 0 1 1 0 7 078000h - 07ffffh 32kb upper 1/16 1 1 0 0 1 0 000000h - 000fffh 4kb lower 1/128 1 1 0 1 0 0 000000h - 001fffh 8kb lower 1/64 1 1 0 1 1 0 000000h - 003fffh 16kb lower 1/32 1 1 1 0 x 0 000000h - 007fffh 32kb lowe r 1/16 1 1 1 1 0 0 000000h - 007fffh 32kb lower 1/16 1 x 1 1 1 0 to 7 000000h - 07ffffh 512kb all
e - cmos corp. ( www.ecmos.com.tw ) page 12 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash table 7. status register memory protection (cmp=1) device identification three legacy instructions are supported to access device identification that can indicate the manufacturer, device type, and capacity (density). the returned data bytes provide the information as shown in the below table. table 8. ECT25S40 id definition table operatio n code m7 - m0 id15 - id8 id7 - id0 9fh e0 40 13 90h e0 12 abh 12
e - cmos corp. ( www.ecmos.com.tw ) page 13 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash instructions description all instructions, addresses and data are shifted in and out of the device, beginning with the most significant bit on the first rising edge of sclk after /cs is d riven low. then, the one byte instruction code must be shifted in to the device, most significant bit first on si, each bit being latched on the rising edges of sclk. see table 9, every instruction sequence starts with a one - byte instruction code. dependi ng on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. /cs must be driven high after the last bit of the instruction sequence has been shifted in. for the instruction of read, fast read, read status register o r release from deep power down, and read device id, the shifted - in instruction sequence is followed by a data out sequence. /cs can be driven high after any bit of the data - out sequence is being shifted out. for the instruction of page program, sector era se, block erase, chip erase, write status register, write enable, write disable or deep power - down instruction, /cs must be driven high exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. that is /cs must driven high whe n the number of clock pulses after /cs being driven low is an exact multiple of eight. for page program, if at any time the input byte is not a full byte, nothing will happen and wel will not be reset.
e - cmos corp. ( www.ecmos.com.tw ) page 14 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash table 9. instruction set t able
e - cmos corp. ( www.ecmos.com.tw ) page 15 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash notes: 1. dual output data io0 = (d6, d4, d2, d0) io1 = (d7, d5, d3, d1) 2. dual input address io0 = a22, a20, a18, a16, a14, a12, a10, a8, a6, a4, a2, a0, m6, m4, m2, m0 io1 = a23, a21, a19, a17, a15, a13, a11, a9, a7, a5, a3, a1, m7, m5, m3 3. quad output data io0 = (d4, d0,..) io1 = (d5, d1,..) io2 = (d6, d2,..) i o3 = (d7, d3,..) 4. quad input address io0 = a20, a16, a12, a8, a4, a0, m4, m0 io1 = a21, a17, a13, a9, a5, a1, m5, m1 io2 = a22, a18, a14, a10, a6, a2, m6, m2 io3 = a23, a19, a15, a11, a7, a3, m7, m3 5. fast read quad i/o data io0 = (x, x, x, x, d4, d0,) io1 = (x, x, x, x, d5, d1,) io2 = (x, x, x, x, d6, d2,) io3 = (x, x, x, x, d7, d3,) 6. security registers address: security register0: a 23 - a16=00h, a15 - a8=00h, a7 - a0= byte address; security register1: a23 - a16=00h, a15 - a8=01h, a7 - a0= byte address; security register2: a23 - a16=00h, a15 - a8=02h, a7 - a0= byte address; security register3: a23 - a16=00h, a15 - a8=03h, a7 - a0= byte address; security regi ster 0 can be used to store the flash discoverable parameters,
e - cmos corp. ( www.ecmos.com.tw ) page 16 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash configuration and status instructions write enable (06h) see figure 5, the write enable instruction is for setting the write enable latch bit. th e write enable latch bit must be set prior to every page program, sector erase, block erase, chip eraseand write status register instruction. the write enable instruction sequence: /cs goes low sending the write enable instruction /cs goes high. figure 5. write enable sequence diagram write disable (04h) see figure 6, the write disable i nstruction is for resetting the write enable latch bit. the write disab le instruction sequence: /cs goes low sending the write disable instruction /cs goes high. the wel bit is reset by following condition:power - up and upon completion of the write s tatus register, page program, sector erase, block erase and chip erase instru ctions. figure 6. write disable sequence diagram read status register (05h or 35h) see figure7 the read status register (rdsr) instruction is f or reading the status register. the status register maybe read at any time, even while a program, er ase or write status register cycle is in progress. when one of these cycles is in progress, it is recommended to check the write in progress (wip) bit before sending a new instruction to the device. it is also possible to read the status register continuo usly. for instruction code 05h, the so will output status register bits s7~s0. the instruction code 35h, the so will output status register bits s15~s8.
e - cmos corp. ( www.ecmos.com.tw ) page 17 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash figure 7. read status register sequence diagram write status register (01h) see figure 8, the write status register instr uction allows new values to be written to the status register. before it can be accepted, a write enable instruction must previously have been executed. after the write enable instruction has been decoded and executed, the device sets the write enable latch (wel). the write status register instruction has no effect on s15, s1 and s0 of the status register. /cs must be driven high after the eighth or sixteen bit of the data byte has been latched in. if not, the write stat us register instruction is not executed. if /cs is driven high after eighth bit of the data byte, the cmp and qe and srp1 bits will be cleared to 0. as soon as /cs is driven high, the self - timed write status register cycle (whose duration is tw) is initiated. while the write status register cycle is in progress, the status register may still be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self - timed write status register cycle, and is 0 when it is completed. when the cycle is completed, the write enable latch is reset. the write status register instruction allows the user to change the values of the block protect (sec, tb, bp2, bp1, bp0) bits, to define the size of the area that is to be treated as read - only, as defined in table 3. the write status register instruction also allows the user to set or reset he status register protect (srp1 and srp0) bits in accordance with the write protect (/wp) signal.the status register protect ( srp1 and srp0) bits and write protect (/wp) signal allow the device to be put in the hardware protected mode. the write status register instruction is not executed once the hardware protected mode is entered. figure 8. write status register sequence di agram
e - cmos corp. ( www.ecmos.com.tw ) page 18 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash write enable for volatile status register (50h) see figure 9, the non - volatile status register bits can also be written to as volatile bits. during power up reset, the non - volatile status register bits are copied to a volatile version o f the status register that is used during device operation. this gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non - volatile bit write cycles or affecting the endurance o f the status register non - volatile bits. to write the volatile version of the status register bits, the write enable for volatile status register (50h) instruction must be issued prior to each write status registers (01h) instruction. write enable for volatile status register instruction will not set the write enable latch bit, it is only valid for the next following write status registers instruction, to change the volatile status register bit values. figure 9. write enable for volatile status regis ter read instructions read data (03h) see figure 10, the read data bytes (read) instruction is followed by a 3 - byte address (a23 - a0), each bit being latched - in during the rising edge of sclk. then the memory content, at that address, is shifted o ut on so, each bit being shifted out, at a max frequency fr, during the falling edge of sclk. the address is automatically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data. this means that the entire memory can be accessed with a single command as long as the clock continues. the command is completed by driving /cs high. the whole memory can be read with a single read data bytes (read) instruction. any read data bytes (read) instructio n, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. normal read mode running up to 50mhz. figure 10. read data bytes sequence diagram
e - cmos corp. ( www.ecmos.com.tw ) page 19 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash fast read (0bh) see figure 1 1, the read data bytes at higher speed (fast read) instruction is for quickly reading data out. it is followed by a 3 - byte address (a23 - a0) and a dummy byte, each bit being latched - in during the rising edge of sclk. then the memory content, at that addres s, is shifted out on so, each bit being shifted out, at a max frequency fc, during the falling edge of sclk. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. figure 11. fast read sequence diagram dual output fast read (3bh) see figure 12, the dual output fast read instruction is followed by 3 - byte address (a23 - a0) and a dummy byte, each bit being latched in during the rising edge o f sclk, then the memory contents are shifted out 2 - bit per clock cycle from si and so. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. figure 12 . dual output fast read sequence diagram
e - cmos corp. ( www.ecmos.com.tw ) page 20 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash quad output fast read (6bh) see figure 13, the quad output fast read instruction is followed by 3 - byte address (a23 - a0) and a dummy byte, each bit being latched in during the rising edge of sclk, the n the memory contents are shifted out 4 - bit per clock cycle from io3, io2, io1 and io0. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. figure 13. quad output fast read sequence diagram dual i/o fast read (bbh) see figure 14, the dual i/o fast read instruction is similar to the dual output fast read instruction but with the capability to input the 3 - byte address (a23 - 0) and a continuous read modebyte 2 - bit per clock by si and so, each bit being latched in during the rising edge of sclk, then the memory contents are shifted out 2 - bit per clock cycle from si and so. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out.
e - cmos corp. ( www.ecmos.com.tw ) page 21 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash figure 14. dual i/o fast read sequence diagram (m7 - 0= 0xh or not axh) dual i/o fast read with continuous read mode see figure 15 , the dual i/o fast read instruction can further reduce instruction overhead through setting the continuous read mode bits (m7 - 0) after the input 3 - byte address (a23 - a0). if the continuous read mode bits (m7 - 0) =axh, then the next dual i/o fast read instruction (after / cs is raised and then lowered) does not require the bbh instruction code. if the continuous read mode bits (m7 - 0) are any value other than axh, the next instruction requires the first bbh instruction code, thus returning to normal operation. a continuous read mode reset instruction can be used to reset (m7 - 0) before issuing normal instruction. figure 15. dual i/o fast read sequence diagram (m7 - 0= axh)
e - cmos corp. ( www.ecmos.com.tw ) page 22 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash quad i/o fast read (ebh) see figure 16, the quad i/o fast read instruction is similar to the dual i/o fast read instruction but with the capability to input the 3 - byte address (a23 - 0) and a continuous read mode byte and 4 - dummy clock 4 - bit per clock by io0, io1, io3, io4, each bit being latched in during the rising edge of sclk, then the memory contents are shifted out 4 - bit per clock cycle from io0, io1, io2, io3. the first byte addressed can be at any location. the address is automatically incremented to the next higher add ress after each byte of data is shifted out. the quad enable bit (qe) of status register must be set to enable for the quad i/o fast read instruction. figure 16. quad i/o fast read sequence diagram (m7 - 0= 0xh or not axh) quad i/o fast read with continuous read m ode see figure17, the quad i/o fast read instruction can further reduce instruction overhead through setting the continuous read mode bits (m7 - 0) after the input 3 - byte address (a23 - a0). if the continuous read mode bits (m7 - 0) =axh, then the next quad i/o fast read instruction (after /cs is raised and then lowered) does not require the ebh instruction code. if the continuous read mode bits (m7 - 0) are any value other than axh, the next instruction requires the first ebh instruction code, thus returning to normal operation. a continuous read mode reset instruction can be used to reset (m7 - 0) before issuing normal instruction. figure 17. quad i/o fast read sequence diagram (m7 - 0= axh)
e - cmos corp. ( www.ecmos.com.tw ) page 23 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash continuous read mode reset (ffh or ffffh) thecontinuous read mode bits are used in conjunction with fast read dual i/o and fast read quad i/o instructions to provide the highest random flash memory access rate with min imum spi instruction overhead, thus allowing more efficient xi p(execute in place) with this device family.the continuous read mode bits m7 - 0 are set by the dual/quad i/o read instructions. m5 - 4 are used to control whether the 8 - bit spi instruction code (bbh or ebh) is needed or not for the next instruction. when m5 - 4 = (1,0), the next instruction will be treated the same as the current dual/quad i/o read instruction without needin g the 8 - bit instruction code; when m5 - 4 do not equal to (1,0), the device returns to normal spi instruction mode, in which all ins tructions can be accepted. m7 - 6 and m3 - 0 are reserved bits for future use, either 0 or 1 values can be used. see figure 18, the continuous read mode reset instruction (ffh or ffffh) can be used to set m4= 1, thus the device will release the continuous re ad mode and return to normal spi operation. to reset continuous read mode during quad i/o operation, only eight clocks are needed. the inst ruction isffh.to reset continuous read mode during dual i/o operation, sixteen clocks are needed to shift in in struction ffffh figure 18. continuous read mode reset sequence diagram
e - cmos corp. ( www.ecmos.com.tw ) page 24 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash fast read quad i/o with 8/16/32/64 - byte wrap around the fast read quad i/o instruction can also be used to access a specific portion within a page by issuing a set burst with wrap(77h)instruction prior to ebh. the set burst with wrap (77h) instruction can either enable or disable the wrap around feature for the following ebh instructions. when wrap around is enabled, the data being accessed ca n be limited to either an 8,16,32 or 64 - byte section of a 256 - byte page. the output data starts at the initial address specified in the instruction, once it rea ches the ending boundary of the 8/16/32/64 - byte section, the output will wrap around to the b eginning boundary automatically until /cs is pulled high to terminate the instruction. the burst with wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/6 4 - byte) of data without issuing multiple read instructions. the set burst with wrap instruction allows three wrap bits, w6 - 4 to be set. the w4 bit is u sed to enable or disable the wrap around operation while w6 - 5 are used to specify the length of the wrap around section within a page. similar to a quad i/o instruction, the set burst with wrap instruction is initiated by driving the /cs pin low and then shifting the instruction code 77h followed by 24 dummy bits and 8 wrap bits, w7 - 0. wrap bi t w7 and the lower nibble w3 - 0 are not used. once w6 - 4 is set by a set burst with wrap instruction, all the following fast read quad i/o and word read quad i/o instructions will use the w6 - 4 setting to access the 8/16/32/64 - byte section within any pag e. to exit the wrap around function and return to normal read operation, another set burst with wrap instruction should be issued to set w4=1. the default value of w4 upon power on is 1. w6 w5 w4 = 0 w4 =1 (default) wrap around wrap length wrap ar ound wrap length 0 0 yes 8 - byte no n/a 0 1 yes 16 - byte no n/a 1 0 yes 32 - byte no n/a 1 1 yes 64 - byte no n/a
e - cmos corp. ( www.ecmos.com.tw ) page 25 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash figure 19. set burst with wrap command sequence id and security instructions read manufacture id/ device id (90h) s ee figure 20, the read manufacturer/device id instruction is an alternative to the release from power - down/device id instruction that provides both the jedec assigned manufacturer id and the specific device id. the instruction is initiated by driving the /cs pin low and shifting the instruction code 90h followed by a 24 - bit address (a23 - a0) of 000000h. if the 24 - bit address is initially set to 000001h, the device id will be read first. figure 20. read manufacture id/ device id sequence diagram
e - cmos corp. ( www.ecmos.com.tw ) page 26 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash jedec id (9fh) the jedec id instruction allows the 8 - bit manufacturer identification to be read, followed by two bytes of device identification. the device identification indicates the memory type in the first byte, and the memory capacit y of the device in the second byte. jedec id instruction while an erase o r program cycle is in progress, is not decoded, an d has no effect on the cycle that is in progress. the jedec id instruction should not be issued while the device is in deep power - down mode. see figure 21, he device is first selected by driving /cs to low. then, the 8 - bit instruction code for the instruction is shifted in. this is followed by the 24 - bit device identification, stored in the memory, being shifted out on serial data output, each bit being shifted out during the falling edge of serial clock. the jedec id instruction is terminated by driving /cs to high at any time during data output. when /cs is driven high, the device is put in the standby mode. once in the stan dby mode, the device waits to be selected, so that it can receive, decode and execute instructions. figure 21. jedec id sequence diagram
e - cmos corp. ( www.ecmos.com.tw ) page 27 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash deep power - down (b9h) although the standby current during normal operation is relative ly low, standby current can be further reduced with the deep power - down instruction. the lower power consumption makes the deep power - down (dpd) instruction especially useful for battery powered applications (see icc1 and icc2). the instruction is init iated by driving the /cs pin low and shifting the instruction code b9h as shown in figure 22. the /cs pin must be driven high after the eighth bit has been latched. if this is not done the deep power down instruction will not be executed. after /cs is driven high, the power - down state will entered within the time duration of tdp. while in the power - down state only the release from deep power - down / device id instruction, which restores the device to normal operation,will be recognized. all other i nstructions are ignored. this includes the read status register instruction, which is always available during normal operation. ignoring all but one instruction also makes the power down state a useful condition for securing maximum write protection.t he device always powers - up in the normal operation with the standby current of icc1. figure 22. deep power - down sequence diagram release from deep power - down/read device id (abh) the release from power - down or device id instruction is a multi - purpose instruction. it can b e used to release the device from the power - down state or obtain t h e devic es electronic identification (id) number. see figure23a, to release the device from the power - down state, the instruction is issued by driving the /cs pin low, shifting the instruction code abh and driving /cs high releas e from power - down will take the time duration of tres1 (see ac characteristics) before the device will resume normal operation and other instruction are accepted. the /cs pin must remain high during t he tres1 time duration. when used only to obtain the device id while not in the power - down state, the instruction is initiated by driving the /cs pin low and shifting the instruction code abh followed by 3 - dummy byte. the device id b its are then shifted out on the falling ed ge of sclk with most significant bit (msb) first as shown in figure 23b. the deviceid value is listed in manufacturer and device identification table.the device id can be read continuously. the instruction is c ompleted by driving /cs high. when used to release the device from the power - down stat e and obtain the device id, the instruction is the same as previously described, and shown in figure 23b, except that after /cs is driven high it must remain high for a time duration of tres2 (see ac characteristics). after
e - cmos corp. ( www.ecmos.com.tw ) page 28 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash this time duration the device will resume normal operation and other instruction will be accepted. if the release from power - down/device id instruction is issued while an erase, program or write cy cle is in process(when wip equal 1) the instruction is ignored and will not have any effects on the current cycle. figure 23a. release power - down sequence diagram figure 23b. release power - down/read device id sequence diagram re ad security registers (48h) see figure 24, the read security registers instruction is similar to fast read instruction. the instruction is followed by a 3 - byte address (a23 - a0) and a dummy byte, each bit being latched - in during the rising edge of sclk. then the memory content, at that address, is shifted out on so, each bit being shifted out, at a max frequency fc, during the falling edge of sclk. the first byte addressed can be at any location. the address is automatically incremented to the next h igher address after each byte of data is shifted out. once the a9 - a0 address reaches the last byte of the register (byte 3ffh), it will reset to 000h, the instruction is completed by driving /cs high. address a23 - a16 a15 - a8 a7 - a0 security registers 1 0 0h 01h byte address security registers 2 00h 02h byte address security registers 3 00h 03h byte address
e - cmos corp. ( www.ecmos.com.tw ) page 29 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash figure 24. read security registers instruction sequence diagram erase security registers (44h) the ECT25S40 provides three 256 - byte security registers which can be erased and programmed individually. these registers may be used by the system manufactu rers to store security and other important information separately from the main memory array. see figure 25, the erase se curity registers instruction is similar to sector/block erase instruction.a write enable instruction must previously have been executed to set the write enable latch bit. the erase security registers instruction sequence: /cs goes low sending erase secur ity registers instruction /cs goes high. /cs must be driven high after the eighth bit of the instruction code has been latched in otherwise the erase security registers instruction is not executed. assoon as /cs is driven high, the self - timed erase security registers cycle (whose duration is tse) isinitiated. while the erase security registers cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self - timed erase security registers cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch bit is reset. the security registers lock bit (lb) in the status register can be used to otp protect the securit y registers. once the lb bit is set to 1, the security registers will be permanently locked; the erase security registers instruction will be ignored. address a23 - a16 a15 - a8 a7 - a0 security registers 1 00h 01h don t care security registers 2 00h 02h don t care security registers 3 00h 03h don t care
e - cmos corp. ( www.ecmos.com.tw ) page 30 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash figure 25. erase security registers instruction sequence diagram program security registers (42h) see figure 26, the program security registers inst ruction is similar to the page program instruction. it allows from 1 to 256 bytes security registers data to be programmed. a write enable instruction must previously have been executed to set the write enable latch bit before sending the program security registers instruction. the program se curity registers instruction is entered by driving /cs low, followed by the instruction code(42h),3 - byte address and at least one data byte on si. as soon as /cs is driven high , the self - timed program security registers cycle (whose duration is tpp) is initiated.while the program security registers cycle is in progress, the status reg ister may be read to check the value of the write in progress (wip) bit.the write in progress (wip) bit is 1 during the self - timed program security registers cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch bit is reset. if the security registers lock bit (lb3/lb2/lb1) is set to 1, the security registers will be permanently locked. program security registers instruction will be ignored. figure 26. program security registers instruction sequenc e diagram address a23 - a16 a15 - a8 a7 - a0 security registers 1 00h 01h byte address security registers 2 00h 02h byte address security registers 3 00h 03h byte address
e - cmos corp. ( www.ecmos.com.tw ) page 31 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash program and erase instructions page program (02h) the page program instruction is for programming the memory. a write enable instruction must previously have been executed to set the write enable latch bit before sending the pag e program instruction. see figure27, the page program instruction is entered by driving /cs low, followed by the instruction code, 3 - byte address and at least one data byte on si. if the 8 least significant address bits (a7 - a0) are not all zero, all trans mitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits(a7 - a0) are all zero). /cs must be driven low for the entire duration of the sequence. the page program instruction sequence: /cs goes low sending page program instruction 3 - byte address on si at least 1 byte data on si /cs goes high. if more than 256 bytes a re sent to the device,previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. if less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. /cs must be driven hig h after the eight h bit of the last data byte has been latched in; otherwise the page program instruction is not executed. as soon as /cs is driven high, the self - timed page program cycle (whose duration is tpp) is initiated. while the page program cycle i s in progress, the status register may be read to check the valu e of the write in progress(wip)bit.the write in progress(wip) bit is 1 during the self - timed page program cycle, and is 0 when it is completed. at some unspecified time before the a page pr ogram instruction applied to a page which is protected by the block protect (sec, tb, bp2, bp1, bp0) is not executed. figure 27. page program sequence diagram
e - cmos corp. ( www.ecmos.com.tw ) page 32 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash sector erase (20h) the sector erase instruction is for erasing the al l data of the chosen sector. a write enable instruction must previously have been executed to set the write enable latch bit.the sector erase instruction is entered by driving /cs low, followed by the in struction code, and 3 - address byte on si. any address inside the sector is a valid address for the sector erase instruction. /cs must be driven low for the entire duration of the sequence . see figure 28, the sector erase instruction sequence: /cs goes low sending 64kb block erase instruction 3 - byte address o n si /cs goes high. /cs must be driven high after the eighth bit of the last address byte has been latched in; otherwise the sector erase instruction is not executed. as soon as /cs is driven high, the self - timed sector erase cycle (whose duration is tse) is initiated. while the sector erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self - timed sector erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch bit is reset. a sector erase instruction applied to a sector which is protected by the block protect (sec, tb, bp2, bp1, bp0) bit is not executed. figure 28. sector erase seque nce diagram 32kb block erase (52h) the 32kb block erase instruction is for erasing the all data of the chosen block. a write enable instruction must previously have been executed to set the write enable latch bit. the 32kb block erase instruc tion is entered by driving /cs low, followed by the instruction code, and 3 - byte address on s i. any address inside the block is a valid address for the 32kb block erase instruction. /cs must be driven low for the entire duration of the sequence. see figure 29, the 32kb block erase instruction sequence: /cs go es low sending 32kb block erase instruction 3 - byte address on si /cs goes high. /cs must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 32kb blo ck erase instruction is not executed. as soon as /cs is driven high, the self - timed block erase cycle (whose duration is tbe) is initiated. while the block erase cycle is in progress, the status register may be read to check the value of the write in p rogress (wip) bit. the write in progress (wip) bit is 1 during the self - timed block erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch bit is reset. a 32kb block erase instruc tion applied to a block which is protected by the block protect (sec, tb, bp2, bp1, bp0) bits (see table 6&7) is not executed.
e - cmos corp. ( www.ecmos.com.tw ) page 33 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash figure 29. 32kb block erase sequence diagram 64kb block erase (d8h) the 64kb block erase instruction is for erasin g the all data of the chosen block. a write enable instruction must previously have been executed to set the write enable latch bit. the 64kb block erase instruction is entered by driving /cs low, followed by the instruction code, and 3 - byte addres s on si. any address inside the block is a valid address for the 64kb block erase instruction. /cs must be driven low for the entire duration of the sequence. see figure 30, the 64kb block erase instruction sequence: /cs goes low sending 64kb block erase instruction 3 - byte address on si /cs goes high. /cs must be driven high after the eighth bit of the last address byte has been latched in; otherwise the 64kb block erase instruction is not executed. as soon as /cs is driven high, the self - timed block e rase cycle (whose duration is tbe) is initiated. while the block erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress(wip) bit is 1 during the self - timed block erase cy cle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch bit is reset. a 64kb block erase instruction applied to a block which is protected by the block protect (sec, tb, bp2, bp1, bp0) bits (se e table 6&7) is not executed. figure 30. 64kb block erase sequence diagram
e - cmos corp. ( www.ecmos.com.tw ) page 34 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash chip erase (60/c7h) the chip erase instruction sets all memory within the device to the erased state of all 1s (ffh). a write enable instruction must be execut ed before the device will accept the chip erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting the instruction code c7h or 60h. the chip erase instruction sequence is shown i n figure 31. the /cs pin must be driven high after the eighth bit has been latched. if this is not done the chip erase instruction will not be executed. after /cs is driven high, the self - timed chip erase instruction will commence for a time duration o f tce. while the chip erase cycle is in progress, the read status register instruction may still be accessed to check the status of the wip bit. the wip bit is a 1 during the chip erase cycle and becomes a 0 when finished and the device i s ready to acce pt other instructions again. after the chip erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the chip erase instruction will not be executed if any page is protected by the block protect ( cmp, sec, tb, bp2, bp1, and bp0) bits (see table 6&7). figure 31. chip erase sequence diagram erase / program suspend (75h) the erase/program suspend instruction allows the system to interrupt a sector or block erase operation, then read fro m or program data to any other sector. the erase/program suspend instruction also allows the system to interrupt a page program operation and then read from any other page or erase any other sector or block. the erase/program suspend instruction sequen ce is shown in figure 32. the write status registers instruction (01h) and erase instructions (20h, d8h, c7h, 60h, 44h) are not allowed during erase suspend. erase suspend is valid only during the sector or block erase operation.if written during the chi p erase operation, the erase suspend instruction is ignored. the write status registers instruction (01h), and program instructions (02h, 32h, 42h) are not allowed during program suspend. program suspend is valid only during the page program operatio n.
e - cmos corp. ( www.ecmos.com.tw ) page 35 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash figure 32. erase/program suspend command sequence erase / program resume (7ah) the erase/program resume instruction 7ah must be written to resume the sector or block erase operation or the page program operation after an erase/program sus pend. the resume instruction 7ah will be accepted by the device only if the sus bit in the status register equals to 1 and the wip bit equals to 0. after the resume instruction is issued the sus bit will be cleared from 1 to 0 immediately, the wip bi t will be set from 0 to 1 within 200 ns and the sector or block will complete the erase operation or the page will complete the program operation. if the sus bit equals to 0 or the wip bit equals to 1, the resume instruction 7ah will be ignored by the device. the erase/program resume instruction sequence is shown in figure 33. figure 33. erase/program resume command sequence
e - cmos corp. ( www.ecmos.com.tw ) page 36 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash electrical characteristics absolute maximum ratings notes: 1.jedec std jesd22 - a114a (c1=100pf, r1=1500 ohms, r2=500 ohms) operating ranges data retention and endurance latch up cha racteristics parameters symbol conditions range unit supply voltage vcc C 0.5 to 4 v voltage applied to any pin vio relative to ground C 0.5 to 4 v transient voltage on any pin viot <20ns transient relative to ground C 2.0v to vcc+2.0v v storage temperature tstg C 65 to +150 c electrostatic discharge voltag e ves d human body model (1) C 2000 to +2000 v parameter symbol conditions spec unit min max supply voltage vcc f r = 108mhz, fr = 50mhz 2.7 3.6 v temperature op erating ta commercial industrial 0 C 40 +70 +85 c parameter test condition min units minimum pattern data retention time 150c 10 years 125c 20 years erase/program endurance - 40 to 85c 100k cycles parameter min max input voltage respect to vss on i/o pins - 1.0v vcc+1.0v vcc current - 100ma 100ma
e - cmos corp. ( www.ecmos.com.tw ) page 37 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash power - up timing figure 34. power - up timing and voltage levels symbol parameter min max unit tvsl vcc(min) to /cs low 10 us tpuw time delay from vcc(min) to write instruction 1 1 0 ms vwi write inhibit voltage vcc(min) 1 2.5 v
e - cmos corp. ( www.ecmos.com.tw ) page 38 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash dc electrical characteristics (t= - 40 ~85 , vcc=2.7~3.6v) note: (1) icc3 is measured with ate loading symbo l parameter test condition min. typ max. unit. ili input leakage curr ent 2 a ilo output leakage current 2 a icc1 standby current /cs=vcc, vin=vcc or vss 13 25 a icc2 deep power - down current /cs=vcc, vin=vcc or vss 2 5 a icc3 current: read single/dual/quad 1mhz sclk=0.1vc c/ 0.9vcc (1) 3/4/5 3.5 /5/6 ma current: read single/dual/quad 33mhz 5/11/19 7.5/12/19.5 ma current: read single/dual/quad 50mhz 6.5/16/30 9.5/17/33 ma current: read single/dual/quad 108mhz 10/33/60 12/35/65 ma icc4 operating current(page program) /cs=vcc 15 ma ic c5 operating current(wrsr) /cs=vcc 5 ma icc6 operating current(sector era se) /cs=vcc 20 ma icc7 operating current(block eras e) /cs=vcc 20 ma icc8 operating current (chip erase) /cs=vcc 20 ma vil input low voltage - 0.5 0.2vcc v vih input high voltage 0.8vcc vcc+0.4 v vol output low voltage iol =100a 0.4 v voh output high voltag e ioh = - 100a vcc - 0.2 v
e - cmos corp. ( www.ecmos.com.tw ) page 39 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash ac measurement conditions figure 35. ac measurement i/o waveform ac electrical characteristics symbol parameter mi n tpy max unit condition s cl load capacitance 30 pf tr, tf input rise and fall time 5 ns vin input pause voltage 0.2vcc to 0.8vcc v in input timing reference voltage 0.3vcc to 0.7vcc v out output timing reference voltage 0.5vcc v symbol parameter min. typ. max. unit. fc clock frequency for all instructions, except read data(03h) dc. 108 mhz fr clock freq. read data instruction(03h) dc. 55 mhz tclh serial clock high time 4 ns tcll serial clock low time 4 ns tclch serial clock rise time (slew rate) 0.1 (1) v/ns tchcl serial clock fall time (slew rate) 0.1 (1) v/ns tslch /cs active setup time 5 ns tchsh /cs active hold time 5 ns tshch /cs not active setup time 5 ns tchsl /cs not active hold time 5 ns
e - cmos corp. ( www.ecmos.com.tw ) page 40 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash note: 1. tested with clock frequency lower than 50 mhz. 2. tw can be up to 45 ms at - 40 during the characterization of the current design. it will be improved in the future design. symbol parameter min. typ. max. unit. tshsl /cs high time read/write 20 ns tshqz output disable time 6 ns tclqx output hold time 0 ns tdvch data in setup time 2 ns tchdx data in hold time 2 ns thlch /hold low setup time (relative to clock) 5 ns thhch /hold high setup time (relative to cl ock) 5 ns tchhl /hold high hold time (relative to clock) 5 ns tchhh /hold low hold time (relative to clock) 5 ns thlqz /hold low to high - z output 6 ns thhqx /hold low to low - z output 6 ns tclqv clock low to output valid 7 ns twhsl write p rotect setup time before /cs low 20 ns tshwl write protect hold time after /cs high 100 ns tdp /cs high to deep power - down mode 0.1 s tres1 /cs high to standby mode without electr onic signature read 3 s tres2 /cs high to standb y mode with ele ctronic signature read 1.5 s tsus /cs high to next instruction after suspend 2 us tw write status register cycle time 10 15 (2) ms tpp page programming time 0.7 2.4 ms tse sector erase time 60 300 ms tbe block erase time( 32k bytes/64k bytes) 0.3/0.5 0.75/1.5 s tce chip erase time 4 10 s
e - cmos corp. ( www.ecmos.com.tw ) page 41 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash figure 36. serial input timing figure 37. output timing figure 38. hold timing
e - cmos corp. ( www.ecmos.com.tw ) page 42 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash ordering information & marking information ec t25s xx x xx x x device function 40 4m bit r tape & reel c commercial(0c to +70c) i:industrial( - 40c to +85c) m1 sop - 8 (150mil) m2 sop - 8(208mil) e1 tssop - 8 p1 pdip s
e - cmos corp. ( www.ecmos.com.tw ) page 43 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash package information sop - 8 l(150mil)
e - cmos corp. ( www.ecmos.com.tw ) page 44 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash package information sop - 8l( 208 mil)
e - cmos corp. ( www.ecmos.com.tw ) page 45 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash package information ts sop - 8l
e - cmos corp. ( www.ecmos.com.tw ) page 46 of 46 4l08 n - r ev. f001 ECT25S40 4m bit spi nor flash package information dip - 8l

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